资源列表
VHDL-Snake-Game-simplify
- Vhdl-Snake game-Vhdl-Snake game........
FPGA_Design_tip
- FPGA设计技巧，锁存器与寄存器区别，状态机设计，门控时钟等-Improving Performance in Complex Programmable Logic Devices (CPLDs) with the FPGA Express Software
cunchuqi
- 利用MAX+PLUS进行存储器设计 并且进行了编译 仿真 得到了波形图-Using MAX+ PLUS for memory design
VHDL-Code---counter
- VHDL Code to desighn a counter
miller
- 用ISE编写的VERILOG语言的米勒解码器的检测部分，检测四种解码信号。程序通过综合，但是仿真结果有点偏差，欢迎高手指点。-ISE prepared with VERILOG language detection decoder Miller of the four decoder signal detection. Procedures through an integrated, but the simulation results is biased and expert advice
EP1C3_12_10_PHAS_PLL
- 这是一个描述pll定值的vhdl语言描述，请大家下载啊-This is a descr iption of the pll value vhdl language descr iption, please download ah
generic_fifo_yh
- Generic, multi-purpose FIFOs. Available as single clock and dual clock version, binary, lfsr, and gray encoded (dual clock only). All are parameterizable and use generic_memories for memory. These FIFOs are fully portable from FPGAs to ASICS.
rs_encoder
- this the code for rs_encoder in verilog-this is the code for rs_encoder in verilog
07070608-2.2
- 利用VHDL语言设计一个分频器，输入为CLK,输出分别为CLK1、CLK8、CLK256、 CLK1024-The use of VHDL language design a divider, input CLK, the output respectively, CLK1, CLK8, CLK256, CLK1024
vmm_log
- vmm log 验证平台，采用vmm搭建-vmm log verification platform, built by vmm
usb_device_core
- usb 设备 IP核 verilog实现-usb device core, verilog
wp_max_flash
- FPGA中FLASH配置控制源码,VHDL和Verilog