资源列表
openfire_core_latest.tar
- openfire实现 microblaze机构的cpu代码,RISC CPU 的Verilog 设计源码，可综合。内含详细的设计文挡-openfire complete microblaze architecture cpu,RISC CPU Verilog sourcecode and documents
VerilogHDL
- 用VERILOG语言总结了常用代码 非常有用
bhas
- this a vhdl program-this is a vhdl program...
ps2verilog
- verilog hdl FPGA PS2时序控制接口源代码 很经典 很实用-verilog hdl FPGA PS2 timing control source code it is very useful and perfect
CH5CH4CH2CH1VHDL 数字电路参考书所有程序5
- CH4CH2CH1VHDL 数字电路参考书所有程序5-CH4CH2CH1VHDL digital circuit reference all proceedings 5
huffnet
- dct based encoding using hufman
ex2
- 驱动四位共阴极数码管数字显示的电路如图所示。该电路采用动态扫描显示技术，当扫描信号的频率大于50Hz时，可显示稳定的四位数码。试采用FPGA器件设计该电路。写出每个模块的VHDL程序；并在相应的EDA仿真工具上进行仿真。-Drive four common cathode LED digital display circuit as shown. This circuit uses dynamic scanning display technology, when the scan signal
simpleDivider
- Divider，VHDL语言，硬件描述语言源码-Divider, VHDL language, VHDL source code
verilogcalculator
- 简易的计算器，可实现加减乘除运算，采用verilog编写-Simple calculator, addition, subtraction operation can be realized using verilog prepared
freq_viewer
- quartusii下基于原理图方式构建的频率计，在altera cyloneIII 芯片上已经验证成功，精度为1Hz-quartusii under way to build a schematic-based frequency meter, in altera cyloneIII chip has proved to be successful, the accuracy of 1Hz
ARM_kernel_verilogHDL
- 这是ARM核心处理器的verilogHDL代码，相当一个软核。-This is the ARM core processor verilogHDL code, is a soft core.
verilog-testbench--technique
- verilog testbench的写法和技巧，适合初学者-Verilog testbench of writing and techniques for beginners