资源列表
CYDOWN
- USB FIFO 测试，为测试USB数据传输的性能-USB FIFO test for the performance of the USB transmit
Bulkloop
- USB FIFO 测试，测试USB的传输性能-USB FIFO test for performance of the USB’s transmission
addersubtractor
- 用verilog语言编写并通过综合验证的加法减法器的工程目录-the design and implementation of addersubtractor using verilog
async_fifo
- 用verilog语言编写并经过综合验证的异步FIFO的源代码-the verilog code of asynchronizing fifo
verilog-testbench-preliminary
- 硬件描述语言verilog的testbench的写作方法-the writing method of the testbench of verilog
modelsim-6.0
- 硬件描述语言仿真工具modelsim 6.0的附图详细教程-the detail tutorial of modelsim 6.0 with pictures
HardCopy
- HardCopy的器件介绍，用于初学者了解ALTERA的器件参数-A descr iption of the Ethernet Tester
ad9854_z1_first
- ad9854的xilinx代码，verilog代码，调试通过的-ad9854 xilinx code, Verilog code, debugging through
armandas-Plong-e2a4bd5
- Plong Game in VHDL Source Code
m_seq
- 产生长度为15的M序列，将m序列产生的数据作为输入，送入一个序列检测器，该序列检测器在检测到连续的“1010”时，送出一个时钟周期宽度的指示信号-15 m_sequence ,and can test"1010"
MyVGA_BouncingBall
- VHDL code for bouncing ball throw VGA port
sin
- 该模块产生以64个时钟为一个周期的正弦波。-The module is a 64 clock cycle of the sine wave.