资源列表
mux2x2_1
- 使用verilog语言在FPGA平台上实现多路选择功能。-The use of Verilog language in FPGA platform to achieve multiple choice function.
basketball24
- 基于FPGA的篮球24秒计时器，开发环境为MAXPLUS-24 second timer in the FPGA-based basketball,Development environment for MAXPLUS
addsub
- 使用verilog语言，在FPGA平台上实现加减法器功能。-The use of Verilog language, in FPGA platform to achieve plus-minus function
10jinzhijishuqi
- 基于fpga的十进制计数器，开发环境为maxpius-Decimal counter fpga-based development environment for maxpius
comparator
- 使用verilog语言，在FPGA开发工具ISE上实现比较器功能。-The use of Verilog language, in FPGA ISE development tools to achieve the comparator function.
kt1
- 基于FPGA的可控100进制可逆计数器，运行环境maxplus-Controlled 100 hex reversible counter FPGA-based operating environment maxplus
flip_flop
- 使用verilog语言，在FPGA开发工具ISE上实现触发器功能。-The use of Verilog language, in FPGA ISE development tools to achieve the flip-flop function.
kt2
- 基于FPGA的交通灯控制系统，红、绿灯按一定的规律亮和灭，绿灯亮时，表示该车道允许通行；红灯亮时，该车道禁止通行。并在亮灯期间进行倒计时，并将运行时间用数码管显示出来。-FPGA-based traffic light control system, red, green, according to certain rules to turn on and off the green light indicates that the lane is allowed to pass red li
exp_cnt_xuehao365_7seg
- 计数器 数码管 3位十进制 exp_cnt_xuehao365_7seg.vhd为顶层文件-Counter digital tube three decimal exp_cnt_xuehao365_7seg. VHD for top level file
timecontrol
- verilog 语言实现巴克码和写串行数据，对PLL进行配置。-using verilog to generate bakema and write series datas for PLL conifgure.
RTThread_uart1
- RTSTREAD实现功能: 利用通用定时器实现定时加一-RTSTREAD functions: the use of general-purpose timers to achieve timing plus a
DE2_70_D5M_LTM_after_SDRAM
- SDRAM作为缓冲器，对采集到的图像进行LTM时时显示-SDRAM as a buffer, the captured image to display LTM