资源列表
vlsi_lab_programs
- this contains the program on verilog-this contains the program on verilog
soccccc
- 此文主要是基于VERILOG HDL 硬件实现的soc系统，主要功能是实现了基于Intel8051的滤波器系统-This article is based mainly on the soc VERILOG HDL hardware system, the main function is to achieve a filter system based on Intel8051
vhdl
- VHDL语言是一种用于电路设计的高级语言。它在80年代的后期出现。最初是由美国国防部开发出来供美军用来提高设计的可靠性和缩减开发周期的一种使用范围较小的设计语言 。-VHDL language is a high-level language for circuit design. It appeared in the late 80' s. Was originally developed by the U.S. Department of Defense for the U.S. mi
FHSSTX
- Frequency Hopping Spread spectrum...Transmitter section
XILINXDual-PortBlockMemory
- xilinx公司的关于双通道存储器的资料。很好很实用的东西。-xilinx company information on the dual-channel memory. Nice and practical.
mul
- multiplier in verilog
adc_spartan.tar
- Spartan 3E-1600 ADC and AMP control.
mizi
- 在文本编辑器下编写用米字数码管显示自定义的的驱动
decoder4_16
- 在文本编辑器下有vhdl语言编写416译码器-In a text editor written in 416 under the decoder vhdl
ISE_lab14
- 采用EDA技术，并应用目前广泛应用的VHDL硬件电路描述语言，实现交通灯系统控制 器的设计。掌握使用VHDL语言设计有限状态机的方法。-With EDA technology and application of the widely used hardware descr iption language VHDL, to achieve traffic light system controller design. Master the use of VHDL language desig
ISE_lab16
- 使用VHDL语言设计数字钟。 数字钟由晶振、分频器、计时器、译码器、显示器等组成-Digital clock design using the VHDL language. Digital clock from the crystal oscillator, frequency divider, timer, decoder, display and other components
sign_by_unsign_multiplication
- sign by unsign and sign by sign multiplication in verilog