资源列表
eda
- 计数器 此程序完成从零开始到9的计数功能呢个 用VHDL语言编写-counter you kan use the program to count from 1 to 9 and the program is free
MLP-network-prior-t-th-FPGA-implementation
- 前向MLP网络的FPGA实现MLP network prior to the FPGA implementation-MLP network prior to the FPGA implementation
Xilinx6EDKtest
- xilinx公司的官方资料，关于EDK试验的。很好的东西。-the company of xilinx official information
ThetrainingcourseofXilinxcompany
- xilinx公司2007年上海培训课程资料，主要是PPT。非常好的资料-xilinx Shanghai in 2007 training material, mainly PPT. Very good information
FPGAandCPLDentry-leveldetailedstudymaterials
- fpga和cpld入门级详细的学习资料，内容很详细很全面。非常实用。-entry-level fpga and cpld detailed study information, the content is more comprehensive. Very useful.
NIOS_UART
- NIOS_LED现成fpgaNIOS系统源代码，运行环境quartus II -NIOS_LED ready fpgaNIOS system source code, operating environment quartus II
banjiaqi_t15
- 这是个半加器,是基于VHDL语言上的操作来实现的!-this is a banjiaqi
shiyan6_1
- 用vhdl语言设计液晶显示14行汉字的程序-Language design using vhdl line 14 character LCD display program
ctc83
- 在文本编辑器中使用VHDL语言设计一个8-3编码器-In a text editor designed using VHDL, a 8-3 encoder
shiyan7_12
- 设计一个数字时钟，具有按秒走时功能，能够分别显示小时（2位24小时）、分种（2位）、秒（2位）的功能，以及整点报警功能-Design a digital clock with seconds to go by when the function that displays hours, respectively (two 24-hour), minutes (2), second (2) function, and the whole point of the alarm function
ISE_lab15
- 利用XILINX官方例程熟悉PicoBlaze软核；熟悉使用Architecture Wizard配置和初始 化DCM；掌握使用核生成器（Core Generate）生成一个IP核，并将其插入到设计中。-XILINX official familiar with the routine use of soft-core PicoBlaze familiar with the Architecture Wizard configuration and initialization DCM
ISE_lab18
- ChipScope软件调试数字系统设计 学会使用ChipScope在线逻辑分析仪工具对设计进行分析； 总结ChipScope软件调试与波形仿真的区别。 -ChipScope software debugging digital system design online learn to use ChipScope logic analyzer tool to analyze the design summary ChipScope software debugging and wa