资源列表
drink_sell_machine
- 用verilog HDL编写的投币机，能实现单种饮料的够买找零-Written in verilog HDL slot machines, enough to buy a single beverage give change
fpga_Stepper-motor
- 通过状态机控制步进电机的转动方向和转动角度-Through the state machine to control the direction of rotation of the stepper motor and the rotation angle
16f630
- hi impedance remote control ir circuits
Synthesis-and-Simulation
- Synthesis and Simulation Design Guide，Xilinx公司的FPGA逻辑综合与仿真，英文版的。-Synthesis and Simulation Design Guide
my-scaler
- 图像缩放源代码，该代码支持输入bmp文件格式，输出bmp格式。-Image scaling source code, which support the input bmp file format, the output bmp format.
dataflow-description
- 这个文件给出了一个四位比较器的数据流描述算法。-This document gives a four comparator data flow descr iption algorithm.
source_file
- 图像传感器数字控制模块，verilog编写，内涵ADC接口，FPGA验证通过。-image sensor digital controller module
I2C_Test
- I2C接口模块，用于连接符合I2C总线接口标准协议的传感器或者其他设备。FPGA验证通过-I2C bus interface
FPGA-clock-for-chess
- 数字电路课程设计 FPAG的棋类时钟设计 -FPGA clock for chess
V0p10
- 完整的基于verilog HDL语言UART代码~-Complete based verilog HDL language UART code to
simple_clock
- 基于ｆｐｇａ的简单时钟，可以作为本科课程设计的内容，用ｖｅｒｉｌｏｇ编写的-Fpga-based simple clock, as the content of the undergraduate curriculum design with verilog prepared
pwm_8
- 8输入来控制八种不同占空比的pwm波产生，分别为12.5 ，25 -8 inputs to control the eight different duty cycle of the PWM wave generating, were 12.5 , 25 ....