资源列表
Designs
- design files in verilog, alu, array mult, carry shift etc.
two_d_dct_serial
- Verilog codes for 2D Discrete Cosine Transform (DCT)
CODING
- VHDL CODE FOR LDPC CODES
lab4
- Verilog lab4 is used for learning vivado
0FGvMPLlST
- 我想要飞的更高扯你扯的蛋都疼了心都慌了但是你还是要20个字(lavifiejflsi laifjl alakdjf)
e_clock
- (1) 具有时、分、秒计数功能，且以24小时循环计时； (2) 计时结果要用6个数码管分别显示时、分、秒的十位和个位 -clock can show time on 24hours,also can show it on h,min and sec
Chapter2
- 通信IC设计的第二章Verilog参考学习代码，方便初学者学习入门，供学习参考用The codes of Chapter1 of《Communication IC Design》-The codes of Chapter2 of《Communication IC Design》
jia-fa-ji-shu-qi
- 含异步清零和同步使能的加法计数器的源代码，用maxplus软件运行，管脚已配置完成，芯片为EP1K30TC144-3-Asynchronous and synchronous cleared with the addition of the counter enable source code, run the software with maxplus Pin has been configured, the chip is EP1K30TC144-3
source
- verilog HDL example .many module .
LIP1756CORE_dsp32_decoder
- LIP1756 DSP32 Decoder verilog source code.
ddr_sdr_V1_1
- DDR控制器 - 用XILINX Virtex II FPGA实现 - 使用DDR MT46V16M16作为仿真模型 - 通用化-DR SDRAM Controller Core - has been designed for use in XILINX Virtex II FPGAs - works with DDR SDRAM Device MT46V16M16 without changes - may be easily adapted
ddr_sdr
- DDR SDRAM Controller Core - has been designed for use in XILINX Virtex II FPGAs - works with DDR SDRAM Device MT46V16M16 without changes - may be easily adapted to any other DDR SDRAM device-DDR SDRAM Controller Core - has been designe