资源列表
interweave_1
- 用VHDL语言编写的实现交织编码和解交织功能的代码。交织采用按行写入，按列读出的方法实现。主要包括：信源信号产生（20位的m序列），交织器，解交织器。为实现流水线的操作，采用了两个交织器和两个解交织器，当一个写入数据的时候，另一个读出数据。-Implementation using VHDL language features Interleaved Coded deinterleave code. Intertwined with by line write, read out by colu
uart
- uart IP CORE Verilog quartus-uart IP CORE Verilog quartusii
8B-10B
- 8b10bencode bianmaqi -8b10bencode bianmaqi jiemaqi
FPGAlearningmaterials
- 大量FPGA学习资料的种子，在此分享了，小弟是呕心呕血拉-A large number of FPGA seed learning materials, to share in this, the boy is pulling hematemesis nausea
nios-2ISP1362
- nios fpga changyong IP Core-nios fpga IP Core
timer16
- 十六进制计数器的的Verilog实现。内有整个工程，包括tb文件。仿真可通过-realizaiton of timer16
lan91c111
- MAC芯片LAN91C111驱动源码，quartus开发环境，Verilog HDL开发语言。自己编写调试通过。对FPGA控制MAC开发者非常有用。-MAC chip LAN91C111 driver source code, quartus development environment, Verilog HDL development language. Write debugging through their own. Very useful for FPGA control MAC d
verilogdesign
- 经典的VHDL资料，北航著名教授的讲稿。
led
- 是基于VERILOG的LED灯控制很简单的-LED lights are controlled based VERILOG very simple
design2
- verilog code for some multiplexers
source
- verilog HDL程序设计教程，随书附赠的源码包，涵盖很多常用模块，内容很全。-verilog HDL programming tutorials, source code packages bundled with the book, covering many commonly used modules are very informative.
vhdYUFA
- 基于VHDL语言的语法，顺序语句和并行语句等等常用语法-无