资源列表
shiftrot
- A verilog hdl code for rotational shift register
pn_code
- 系数为4的扰码生成器，并每四位扰码产生一个触发串并转换的触发信号，可用于4b/5b编码的触发信号。verilog程序，带test程序-coefficient of the four scrambler generator, and every four scrambler have triggered a string conversion and the trigger signal can be used to trigger 4b/5b coding signal. Verilog pro
mp3_decoder
- mp3VHDL语言程式，这是一个关于mp3 播放的程序的程序，是我从同学那里拷过来的，试了一下
ping_pong_buffer
- 用寄存器来实现乒乓缓存(Verilog HDL)-Ping-pong with the register to achieve cache (Verilog HDL)
T
- T触发器 T触发器VHDL实现及报告 FPGA-T flip-flop VHDL implementation and reporting.
LIP1602CORE_des
- Verilog DES Encrption Module
tel
- 电话用户信令控制器的VHDL实现-Telephone subscriber signaling controller based on VHDL
USB枚举
- ALTERA NIOS处理器实验，编程环境是QUARTUS，在NIOS SHELL下编译实现功能。实验USB接口-Altera NIOS processor experiments, programming environment is QUARTUS in NIOS SHELL compiler functionality. Experimental USB interface
spislave_latest[1].tar
- Serial Peripheral Interface Slave interface
F_adder
- 这个源程序是关于全加器的，又需要的同学可以借鉴一下 -This source code is on the full adder, and also the needs of students can learn from you
you_ran
- 串行UART接收，采用VHDL语言，供参考-Universal Asynchronous Receiver/Transmitter
linijka
- linijka--pomiarowa.rar Generalnie w odbiorniku nie ma wiekszel filozofi. Sa sygnaly z 2 czujnikow, zaluzmy ze czujnik 1 jest po lewej stronie, 2 po prawej. Czyli (zgodnie z tym opisem www.elektroda.pl/rtvforum/topic1132763.html) jeli z 2-giego czuj