资源列表
SingleChipDigitalClock
- 单片机数字钟程序，其中包含闹铃功能，基于51单片机-Single chip digital clock program, which includes an alarm function, based on MCU 51
45666001shzdyb
- 数字电压表的实现，运用vhdl语言，进行仿真-digital
Multiplexer-Description2
- 通过应用QUARTUSII开发软件对 四选一多路选择器进行设计，并给出运行结果-Software development through the application of QUARTUSII choose one of four multiplexer design, and operating results are given
gps_tracking
- 澳大利亚新南威尔士大学研究的GPS接收机的FPGA跟踪模块的.v程序，包括载波跟踪环路、码跟踪环路、通道累加等模块。-The University of New South Wales, Australia, the study of the FPGA tracking GPS receiver module. V procedures, including the carrier tracking loop, code tracking loop, the channel accumulati
shzdyb
- 这是在FPGA上实现的数字电压表，用VHDL编写的，已通过编译，仿真验证。-This is the FPGA to achieve the digital voltage meter, prepared by using VHDL, compile and simulation.
fir_filter
- 采用vhdl语言在Altera的开发板DE2-70上实现的低通滤波器的工程-Vhdl language used in the Altera DE2-70 development board to achieve the low-pass filter project
RISC_CPU
- Verilog HDL编写的一个精简指令的处理器，很好用，可用来学习-Verilog HDL RISC_CPU
猜數字，終極密碼
- verilog code 可以控制玩家數目，及遊戲模式(有兩種:猜數字 + 終極密碼) 最後結果會顯示出排名及分數
Teletext_Core_Files_890607
- A teletext extraction source code for WST PAL B standard
crack_qii90
- altera quartus 9 crack working
Async_fifo_verilog
- FIFO的用途，分类，一些重要参数，设计的难点和算法-FIFO uses, some important parameters, the difficulty of the design and algorithm
pingpangqiu
- 用max+plusII编写的vhdl程序 乒乓球游戏机-with max plusII vhdl procedures for the preparation of the table tennis game