资源列表
asynchronous-FIFO-verilog
- FIFO是英文First In First Out 的缩写，是一种先进先出的数据缓存器，他与普通存储器的区别是没有外部读写地址线，这样使用起来非常简单-FIFO is an abbreviation of the English First In First Out, is a first-in, first-out data buffer, the difference between him and ordinary memory is external read and write add
source
- SDRAM通用接口程序，和Altera所给标准一致
src
- 频率综合器 数字控制寄存器 verilog 代码-Digital Frequency Synthesizer Control Register verilog code
fir_filter
- 使用Verilog编程实现的分布式FIR滤波器源码，经过调试能够完成功能-Distributed programming using the Verilog source code FIR filters, after a debugging feature to complete
Bist_codings
- In this paper, we have explained the purpose of FPGA testing. A built-in-self-test (BIST) is one type of testing. This test is performed internally to find any faults within a FPGA chip. This paper explains why testing is important to FPGAs. It also
UART
- verilog hdl UART de bo xing-verilog
carry_ripple_adder
- carry ripple adder vhdl code
memory_cores2.tar
- 内存的硬件语言描述，特别好的。比较适合做IC设计的开发人员。
W25Q16_verilog_ise
- 一个基于w25q16的四通道flash读写操作控制器，spi传输。verilog语言编写，在ise的chipscop上验证可行，仅作学习参考-this is refrence about flash w25q16 controller ，writed by verilog
fx2lp_slaveFIFO
- 一种基于quartus下的labview开发驱动 将代码用到原理图中 可以进行下位机与上位机之间的读取与上传-fifo driver
Describe-counter
- 通过应用QUARTUSII开发软件对用if语句描述二进制（M＝10）计数器进行设计，并给出运行结果-Software development through the application of QUARTUSII if statement with the descr iption of the binary (M = 10) counter design and operation results are given
UART
- 用VHDL语言编程实现UART，8位数据位，校验位自己可以加！LIBERO仿真正确！-VHDL language programming with UART, 8 data bits, parity bit that they can add! LIBERO simulation correctly!