资源列表
DDS
- 直接数字频率合成器dds，用verilog实现，经过quartus验证-Direct digital frequency synthesizer the dds, used verilog achieved after quartus verify
fenping16
- 十六分频verilog代码，经过quartus验证-16 divided verilog code verification after quartus
freq
- 等精度频率计的verilog实现，经过quartus编译-Verilog to achieve equal precision frequency meter
traffic-light
- Verilog based traffic light controller source code
drink-machine
- Verilog codes for drink machine design project codes
async-fifo
- Verilog codes for asynchrounous fifo design
cascaded-muliplier
- Verilog based for cascaded multiplier design-Verilog based for cascaded multiplier design
fpga-vhdl-lcd1602
- fpga 1602测试程序 vhdl语言-fpga 1602测试程序
setled
- fpga vhdl花样流水灯测试程序简单流水灯-Fpga VHDL pattern of flowing water light test procedure
Hamming
- Hamming Encoder of 7bit in VHDL, Where it consists 3 parity bits and 4 data bits, then after it is being passed to decoder where it corrects, if their is any error and gives desired data as output. -Hamming Encoder of 7bit in VHDL, Where it consist
vhcg_latest.tar
- Viterbi algorithm is the most likelihood decode algorithm of convolution code. Viterbi decoder means the VLSI implementation of Viterbi algorithm. In the area of communication, convolution code is very popular, so how to improve the performance a
I2C
- I2C总线的FPGA实现,Verilog语言实现!-FPGA implementation of the I2C bus, Verilog language realize!