资源列表
firfilter
- FIR滤波器 用VHDL程序实现数字信号输入后的有限长单位冲激响应滤波,进而再进行其他信号处理-FIRfilter Using VHDL to realize the fir filter
LDPCtest
- ldpc编码器ru算法的verilog语言的完整实现，希望对您有用-ldpc encoder, RU, VERILOG，altera
fred
- FPGA等精度测量 程序，已仿真通过。-FPGA and precision measuring program, already through simulation.
SP
- 这是一个有状态机写成的售票系统，可以实现售票找零等功能-This is a state machine written in the ticketing system, you can achieve the ticketing change for functions
使用VHDL语言实现74LS147功能
- 使用VHDL语言实现74LS147功能，简单易懂，方便学习与理解。-Use the VHDL language 74LS147 function, easy-to-understand, facilitate learning and understanding.
BASYS_DDS
- fpga 实现dds,共享给大家了，如果有问题请交流，-fpga implementation dds, for everyone to share, if there is a problem, please exchange, thank you
等精度数字频率计使用VERILO语言实现
- 等精度数字频率计使用VERILO语言实现，大家可以-To such precision digital frequency the meter use VERILO language, we can see
等精度数字频率计
- 等精度数字频率计，大连理工大学创新学院，看看吧-And other precision digital frequency meter, Dalian University of Technology Innovation Institute, take a look at it
vga
- vga 使用vhdl语言实现一张图片的显示，具有完整的工程及源代码，下载验证通过（注意硬件差别）-vga vhdl language to display a picture, have a complete engineering and source code, download the verification (note the hardware differences)
E2_4_SimSigPrduce
- 混频器 利用FPGA实现625khz乘以625khz混频器的设计-mixer come ture 625khz*625khz
num-seven
- 16位加法器，采用行为描述的建模方式进行建模的加法器-16 bit adder
CY7C68013-GPIF-PA0-PA1
- VC控制CY7C68013脉冲发出，PA0\PA1发出-The VC control CY7C68013 pulse issue, PA0 \ PA1 issued