资源列表
PR-user-guide12.3
- 可重构fpga用户使用指南，详细介绍开发流程。-Reconfigurable fpga user guide, detailing the development process.
marquee
- Multisim11下8051跑马灯仿真。-The 8051 Marquee under Multisim11 simulation.
project1source
- sdh帧同步，实现sdh帧搜索，预同步，同步，保护等各态的功能-SDH frame synchronization SDH frame search, pre-sync, synchronization, protection, the function of each state
FPGA_LCD_BEST
- FPGA液晶驱动程序，调试通过，可以直接在硬件上跑-This code is directly through debugging in hardware to run
vhdl_text3
- 设计一个数据宽度8bit，深度是16的 同步FIFO(读写用同一时钟)，具有EMPTY、FULL输出标志。 要求FIFO的读写时钟频率为20MHz， 将1－16连续写入FIFO，写满后再将其读出来（读空为止）。 仿真上述逻辑的时序-Design a data width 8bit depth of 16 the synchronization FIFO (read and write with the same clock), EMPTY, FULL output fla
led_display
- 用fpga芯片实现7段数码管静态显示7128-Using the fpga chip realize 7 period of digital tube static display 7128
lcd_driver
- 在1602液晶模块上显示字符串，其中第一行显示“Welcom to hx" 在第二行显示“www.mcuhx.com- in 1602 LCD module display on a string, including the first line shows "Welcom to hx" In the second row shows "www.mcuhx.com
div_5
- 用Verilog语言写五分频电路，占空比为50％-language to write fifth frequency circuit, the duty cycle of 50
four_adder
- 通过调用被实例化的模块来实现四位全加器功能-Four full adder function is achieved by calling the module is instantiated
SAYEH
- Verilog 数字系统设计---综合、测试平台与验证 .书中源程序-cpu in verilog descr iption. include C language source
fpga_msp430
- fpga和msp430进行通信，包括他们之间的通信协议-Fpga and msp430 in communication，Including the communication protocol between them
jishuqi
- 在fpga实验版上实现4位7段数码管动态显示，数字递增-In fpga experimental edition to realize four 7 period of digital tube dynamic display, digital increasing