资源列表
clk
- 基于EP2C5Q208C的二分频verilog代码，modelsim仿真及下载配置-Verilog code, modelsim simulation and download configuration based on EP2C5Q208C binary frequency
round
- 利用实验箱标配的AD_DA板上的D/A数模转换器，模拟一个圆的波形，学习LPM_ROM（1024*10）宏功能模块的定制与使用，最后利用Quartus II完成设计、仿真。-The the experimental box standard AD_DA panel D/A converters, a round analog waveform, learning LPM_ROM (1024* 10) the megafunctions the customization and use last
data_to_asc
- 将二进制文件如图片转换为文本文件,用于FPGA的数表-translate binary to ASICII
asc_to_raw
- 将文本文件转换为二进制文件如图片,用于FPGA的数表-from text to binary file
stream_to_asc
- 将二进制码流转换为ASICII文件,可做fpga码表-from bianry streams to ASICII
a-to-A
- 将字符串转换为ASICII，用于FPGA码表-from strings to ASICII
tsxt4
- 频率计，使用Fpga的语言设计实现对频率的测量，可以通过自己修改，平台式ED2 开发板》-Frequency meter, the use of Fpga language design and implementation of frequency measurement, can modify their own, platform type ED2 development board "
niosII_cycloneIII_3c120_fast
- nois2 开发实例。应用平台是DE2开发板。实现一个简单的电子时钟的显示万年历。设计简单，便捷-Frequency meter, the use of Fpga language design and implementation of frequency measurement, can modify their own, platform type ED2 development board "
www_onlylz_com@b-do84mw
- nois2 开发实例。应用平台是DE2开发板。实现一个简单的电子时钟的显示万年历。设计简单，便捷-nois2 development instance. The application platform is DE2 development board. Implement a simple electronic clock display calendar. The design is simple, convenient
VGA
- 用Verilog HDL编写的VGA显示程序，可实现图像的显示，在DE2-70上测试通过，有很大的参考价值。-Prepared using Verilog HDL VGA display program, image display DE2-70 test by great reference value.
uart
- 用Verilog HDL编写的串口输入输出程序，可实现数据的传输，在DE2-70上测试通过，有很大的参考价值。-Prepared by the serial input and output using Verilog HDL program can achieve data transmission test by DE2-70, there is a great reference value.
sdram_mdl
- 用Verilog HDL编写的SDRAM控制程序，在DE2-70上测试通过，有很大的参考价值。-SDRAM control program written using Verilog HDL DE2-70 test passes, great reference value.