资源列表
HDB
- FPGA实现HDB3码的编码与译码 采用EDA工具中的Quartus II 8.1作为软件平台，实现HDB3码数字基带信号的编码和译码。-FPGA Implementation of the HDB3 code encoding and decoding using Quartus II 8.1 EDA tools as a software platform, achieve the encoding and decoding of the HDB3 code digital baseba
VHDL--traffic-light-reports-and-code
- 用VHDL实现交通灯项目，并用FPGA验证！-The traffic light project using VHDL and FPGA verification!
VHDL-stopwatch-reports-and-code
- 用VHDL实现数字秒表的设计实践，并用FPGA下载进行功能验证！-Using VHDL the digital stopwatch design practice, and functional verification of FPGA download!
VHDL-counter-code
- 用WHDL实现计数器的各个模块设计，并用FPGA进行功能验证！-With WHDL counter module design and functional verification using FPGA!
VHDL-music-generator-report-code
- VHDL实现音乐发生器,并进行FPGA验证！报告中含有各模块详细代码，和仿真波形！-VHDL music generator and FPGA verification! The report contains a detailed code of each module, and the simulation waveform!
FPGACPLD-design-tools-Xilinx-ISE
- FPGA/CPLD设计工具──Xilinx ISE使用详解！x详细介绍了XilinxISE的使用方法！-FPGA/CPLD design tools ─ ─ Xilinx ISE explain the use of! x details use XilinxISE!
UART-based-on-FPGA
- UART的FPGA的实现，有工程和设计文档说明-FPGA implementation of the UART, engineering and design documentation for instructions
S7_PS2_LCD
- 1、ps/2键盘输入，通过led显示ascii码 2、稍等1s可以在lcd上显示输入的字符 3、其中键盘上的backspce键是用来清屏的 4、当lcd上显示满字符时，在按下按键自动清屏，从第一行显示。-1, ps/2 keyboard input, through the led display ascii code 2, wait 1s in the lcd display input characters, of which the the keyboard on backsp
S6_VGA
- 1。源文件保存在src目录，QII的工程文件保存在Proj目录； 2。程序实现的功能是在VGA显示器上显示彩色条纹，共8种颜色， 可以使用嵌入式逻辑分析仪观测信号； 3。modelsim仿真文件在proj--simulation--modelsim中-1. The source file is saved in the src directory QII project file is saved in the directory Proj 2. The functionalit
S3_WAVE
- 1、本实验模拟正弦函数发生器 2、使用逻辑分析仪查看波形 3、/proj/simulation目录中可以在modelsim中仿真-1, the experimental simulation of the sine function generator, logic analyzer view waveform 3/proj/simulation directory in modelsim simulation
the_design_basedonfpga
- 1. clkdiv 介绍时钟分频器的建模 2. counter 介绍计数的建模 3. dtrig 介绍D触发器的建模 4. jktrig 介绍JK触发器的建模 5. shiftreg 介绍移位寄存器的建模 6. ttrig 介绍T触发器的建模-The 1. Clkdiv modeling clock divider 2. Counter introduced count modeling the The 3. Dtrig 4. Jktrig introduce the mod
duanx
- 实现超简洁、超清晰的 任意整数分频器功能，完全自己编制的。代码清晰了然，且占用自然少。完全适合调用。-Achieve ultra-simple, ultra-clear any integer divider function fully prepared in. Code is clearly understood, and naturally less occupied. Perfectly suited to the call.