资源列表
my_clock
- 使用verilog HDL语言编写的时钟电路代码，能实现24小时电子钟的功能。-Using verilog HDL code written in the clock circuit can achieve 24-hour clock function.
p4_adder.tar
- 用vhdl实现的P4加法器，包括主要元件rca加法器，carry select adder,pg模块，并提供了一个测试文件，用modelsim测试通过-P4 adder implemented using VHDL, including the major component such as: rca adder, carry select adder, pg module,in addition provides a test file, all modules have been teste
74ls165
- 74ls165电路源代码verilog,已经验证。-74ls165 verilog
74ls138
- 74ls138电路的verilog源代码，已经验证。-74ls138 circuit verilog
74ls109
- 74ls109电路的VERILOG源代码，已经验证-74ls109 circuit
dds5.0
- DDS电源设计，使用时须将SIN_ROM.VHD中的LPM_FILE修改为个人MIF文件的路径，本套程序中包含多个MIF文件，注意选用合适的文件。-DDS power supply design, use of LPM_FILE SIN_ROM.VHD shall modify the path for personal MIF file, this set of procedures in multiple MIF files, pay attention to choose the appr
mips
- MIPs CPU，VERILOG代码，经过QUARTUS综合，时序分析，验证无误。-MIPS CPU
bayindianziqin
- EDA课程设计，Verilog写的电子琴程序，已经联合硬件调试成功。-EDA curriculum design, Verilog was the flower program, has successfully combined hardware debugging.
jtdVHDL
- 用VHDL语言完成了一个交通灯的设计 设计较简单 一看就明白-VHDL language used to complete the design of a traffic light design relatively simple to understand at a glance
Traffic_Light_Controller_Test_Bench
- VHDL Test Bench For Traffic Light Controller
Traffic_Light_Controller
- VHDL Code for traffic Light Controller
LCD
- VHDL LCD Interface Code