资源列表
IEEE-Std-1076.6-1999-VHDL-RTL-Synthesis
- IEEE Std 1076.6-1999 VHDL RTL Synthesis
Xcell-Journal-issue-82
- Xcell Journal issue 82 released by Xilinx.
dianti
- 基于FPGA的六层电梯控制模型 内含波形仿真图形-FPGA-based six-story elevator control model includes a waveform simulation graphics
SSDT
- 同步串行数据发送电路，并行数据输入，串行数据输出。-Synchronous serial data transmission circuit, parallel data input, serial data output.
lab1
- 一个21位先行进位加法器的代码 交作业和毕设必备，自己写的，不完全地方请指出 -A 21-bit carry-lookahead adder code homework and must complete set up, wrote it myself, not exactly place please indicate
motor
- 课程设计 直流电机 pwm verilog -Curriculum design DC motor pwm verilog
cpu
- 简易cpu 课程设计 vhdl modelsim-Easy cpu curriculum design vhdl modelsim
step-moto
- 步进电机 细分/非细分 verilog -Stepping Motor/Non subdivision verilog
dds
- 利用FPGA实现分频，实现DDS分频模块 -Divide using FPGA realize DDS frequency module
EP3C40EDA_Exp31_SAD_DA_Test
- CycloneIII系列芯片EP3C40F780C8 SAD_DA 实验工程代码-CycloneIII，EP3C40F780C8，SAD_DA code
EP3C40EDA_Exp30_HAD_DA_Test
- 选用CycloneIII系列芯片EP3C40F780C8，HAD_DA实验代码-CycloneIII，EP3C40F780C8，HAD_DA code
EP3C40EDA_Example29
- 选用CycloneIII系列芯片EP3C40F780C8，mouseTest实验代码-CycloneIII，EP3C40F780C8，mouseTest code