资源列表
seven_color
- FPGA产生7条竖色条，分别是7个基本色。并显示到VGA接口的显示器-FPGA generate seven vertical color bar are seven basic colors. And display monitor to the VGA port
div_clk
- 一个20M转16M的时钟分频设计的小程序。有一定的漏洞请大家自行修正-A 20M to 16M clock frequency applet. There are some loopholes Please correct itself
pri_encoder_using_if
- encoder using if - verilog
decoder_using_with
- decoder_using_with verilog code
EDA
- 4位十进制计数器+7段数码管显示,有需要的同学可以参考一下！-4 decimal counter+7 of segment LED display
product-Altera
- ALTERA 产品列表，内有详细参数，用于设计时参考选型-altera products for selecting
Digital_Clock
- FPGA数字时钟完美通过测试。目标板是ZRTECH的EP2C5T144C8 CORE2-5U核心板及PERI1-8KD配套子卡。-The FPGA digital clock perfect pass the test. The target board is ZRTECH EP2C5T144C8 CORE2-5U core board and PERI1-8KD supporting daughter card.
sdram
- SDRAM控制程序！verilog语言，已调通！-The SDRAM control procedures! Verilog language, has been transferred through!
DA_TLC56201
- 基于FPGA芯片，应用verilog hdl语言编写DA_TLC5620芯片，实现相应功能的源程序。-FPGA-based application Verilog HDL language DA_TLC5620 chip, the corresponding function of the source.
LCD12864
- FPGA控制带字库型12864显示，本程序使用状态机实现状态翻转-The FPGA control with a character type 12864, the program uses state machine state flip
hanzi0430
- 基于FPGA芯片，在16x16的点阵上滚动重复显示多个汉字的源代码-Repeated 16x16 dot matrix rolling display the source code of Chinese characters based on the FPGA chip,
dc_rmv
- 这是一个用verilog写的DC滤波器，即melp算法中预处理部分，主要滤除50hz工频干扰，采用一个4阶的切比雪夫高通滤波器，截去频率位60hz以下的信号，其阻带的衰减位30db。-This is a verilog to write a DC filter the preprocessing part that melp algorithm, main filter 50hz frequency interference, the use of a fourth-order Chebyshe