资源列表
UART-by-Verilog
- 用Verilog实现UART，并且附有详细说明那个-The Verilog UART, and with the detailed descr iption that
EDA-xiti
- 由12进制和60进制计数器组成的时钟电路。-12 229 and 60 binary counter clock circuit.
tutorial1
- Example of VHDL. How to start with VHDL concepts.
procesador_1
- VHDL project of a small CPU
amb-cui_current_filter1211
- 确实可用的电机用死区控制程序，已验证稳定性-Motor control deadband control
dds_work
- verilog语言编写，在Quartus II里仿真DDS的产生，包括所有仿真生成的相关文件--verilog language in the Quartus II DDS in the generation of simulation, including all documents generated by the simulation,
FIFOverilog
- 异步FIFO实现数据先入先出的存储方式基于verilog HDL语言-Asynchronous FIFO first-in, first-out data storage based on Verilog HDL language
8051_PLJ
- 本设计基于8051IP Core和FPGA技术结合提出一种等精度频率测量方案，解决了传统测频方法测频精度随频率的下降而下降的问题。-The design is based 8051IP Core and FPGA technology combined proposes a precision frequency measurement solutions solve the traditional frequency measurement frequency measurement accu
my_uart
- 本程序采用Verilog HDL程序编写的串口程序。-The program uses the Verilog HDL programming serial procedures.
IEEE-Std-1364.1-2002-Verilog-RTL-Synthesys
- IEEE Std 1364.1-2002 Verilog RTL Synthesys
IEEE-Std-1364-2001-Verilog-LRM
- IEEE Std 1364-2001 Verilog LRM
IEEE-Std-1800-2012-SystemVerilog
- IEEE Std 1800-2012 SystemVerilog - Unified Hardware Design, Specification, and Verification Language