资源列表
VGA-color-signal-generator
- 1． 了解普通显示器正确显示的时序。 2． 了解VHDL产生VGA显示时序的方法。 3． 进一步加强对FPGA的认识。 -1. Learn ordinary display correctly display timing. 2. Learn VHDL VGA display timing generation method. 3. Further enhance the understanding of the FPGA.
CIII_EP3C40F780C8_35_FAT_SDcard
- SOPC,CycloneIII系列芯片EP3C40F780C8，NIOS II IDE,FAT_SDcard 实验代码 -SOPC,CycloneIII，EP3C40F780C8，NIOS II IDE, FAT_SDcard code
sdram_mdl
- 基于verilog的SDRAM读写控制,源自特权同学-SDRAM controller use to read or write base on verilog，it is from teqian
VHDL-design-seven-people-voting
- 1、 熟悉VHDL的编程。 2、 熟悉七人表决器的工作原理。 3、 进一步了解实验系统的硬件结构。 -1, familiar with VHDL programming. 2, familiar with the seven voting machine works. 3, to further understand the experimental system hardware architecture.
VHDL-design-four-Responder
- 1、熟悉四人抢答器的工作原理。 2、加深对VHDL语言的理解。 3、掌握EDA开发的基本流程。 -A familiar four Responder works. 2, to deepen the understanding of the VHDL language. 3, master EDA development of the basic processes.
m4kvgachar
- 基于M4K的字符VGA显示，来源于特权同学-M4K based VGA display characters, from the privileged students
cof_M4K_test2
- 基于M4K块的移位寄存器配置仿真,来源于特权同学-M4K blocks based on the shift register configuration simulation, students from privileged
vgachar
- 基于verilog的VGA字符显示，肯定好使-The VGA display characters based on verilog, so that certainly
src
- 基于FPGA的频谱分析仪，使用VHDL语言描述，源代码-FPGA-based spectrum analyzer, using VHDL language descr iption, source code
BayesShrink_RGB
- wienerfilter for image
Digital-frequency-meter
- 1. 了解等精度测频的方法和原理。 2. 掌握如何在FPGA内部设计多种功能模块。 3. 掌握VHDL在测量模块设计方面的技巧。 -1 understand other precision frequency measurement methods and principles. (2) learn how to design a variety of functions within the FPGA module. 3 master VHDL module design aspec
Multi-function-digital-clock
- 1、 了解数字钟的工作原理。 2、 进一步熟悉用VHDL语言编写驱动七段码管显示的代码。 3、 掌握VHDL编写中的一些小技巧。 -1, to understand digital clock works. 2, more familiar with the use of VHDL language driver seven segment display code. 3, master VHDL prepared some of the tips.