资源列表
5fenpin
- vhdl的时钟信号分频 5分频电路代码 将任意频率5分频-vhdl clock signal frequency divider circuit 5 code any frequency band 5
Chapter-5
- Verilog数字系统设计教程(第2版)”这本书的思考题没有答案，要多做实验和仿真-• Source code of designs in chapters 1 to 8. • Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files. • Several Designs, including SAYEH, that are
sdramctrl
- sdram controller vhdl
Building-Counters-Veriog-Example
- building counters in vhdl
tstbench
- pci 接口协议 用Verilog编写，经过测试使用，与大家共享
vhdl
- 这是一些经典的vhdL源代码，这些代码，用于嵌入式学习，对于想学vhdL的同学很有帮助-This is some classic vhdL source code, the code, for embedded study, is very helpful for students want to learn the vhdL
Cronometro_DE0
- VHDL for a chronometer implemented into the DE0 board of terasic.
alu-div
- 用verilog HDL代码编写的快速除法器，比较有用
deinter
- deinterlace的核心verilog，
123
- 一个汉字显示源程序，关于用VHDL,大家可以参考一下-A Chinese character display source code using VHDL, we can refer to
alt_flash_prog
- 这是在ALTEAR上使用的代码。他是用来NOIS II开发的代码。可以用的。
AD9851-cuan
- 非常好用的51单片机驱动DDS AD9851串行程序，已编译通过，能过使用！-Very nice 51 Microprocessor DDS AD9851 program, compiled by, can live with!