资源列表
derotator
- derotator for qam with sin and cos lut
additionneur4_bits.tar
- It s a VHDL code source to implement the 4 bits additionor in VHDL
char.tar
- 传输线路逻辑，采用first in first out 算法进行data传输-fifo
pipeline_code
- 实现了MIPS五级流水CPU,用verilog语言实现-MIPS CPU verilog
ef48dc75a9a60030c622898a19b0f2d6 (1)
- 内有关于循环码的编码器的程序语言，可用quartus ii打开(There is a program language on the encoder of the loop code, which can be opened with Quartus II)
kdtree-scala-master
- Kd tree implementation in scala spark language
fifo
- 基于verilog HDL的fifo设计与测试，包含设计与测试代码，以及简单的makefile编写。整个平台是基于linux操作，仿真平台是基于SYNOPSYS的vcs工具。(Based on verilog HDL fifo design and testing, including the design and test code, and simple makefile.The platform is based on Linux operating, the simulation pla
数字钟
- 数字钟(Digital clock)
SPI
- 用Verilog语言实现FPGA串口通信(Using Verilog language to realize FPGA serial communication)
aes_128pprm3
- 基于PPRM3S盒的128位AES密码算法Verilog代码(Verilog code for 128 bit AES cipher based on PPRM3S box)
FPGA实现AD8556采集程序设计
- 基于ADS8556的FPGA数据采集程序设计。(The design of FPGA data acquisition program based on ADS8556.)
RS(204,188)译码器的设计
- RS(204,188)译码器说明 原文件： rs_decoder.v（顶层文件）, SyndromeCalc.v（计算伴随式）, BM_KES.v（BM求解关键方程）, Forney.v（Forney算法求误差样值）, CheinSearch.v（搜索错误位置）,ff_mul.v（有限域乘法）。 ROM及初始化文件： rom_inv.v（求逆运算）, rom_power.v（求幂运算）； rom_inv.mif（ROM初始化文件）, rom_po