资源列表
UART
- UART receiver transmitter verlog code
LMS-vhdl-coad-
- 基于quartus的LMS 自适应滤波器代码，适合初学者 -The LMS adaptive filter based on quartus code, suitable for beginners
bouncing_ball
- vga输出跳动小球代码，采用vhdl编码，通用各种fpga期间-vga outputs bouncing ball
stopwatch_verilog
- 数字跑表 verilog语言设计有开始 有暂停 顺序计数-stopwatch verilog
calling-cost-program
- 电话计费FPGA程序，作为一个简单开发FPGA不错的程序，希望对大家有用。-Telephone billing FPGA program developed as a simple FPGA good program, we hope to be useful.
BMD.RAR
- xilinx BMD ver 10 pciexpress testbench for master design
MAXPLUSII
- MAX+PLUSII使用说明 很具体是初学者的必读之物-MAX+ PLUSII use are very specific reading of material for beginners
rs_decoder_31_19_6
- 里的所罗门RS编解码方案，建立工程后可直接编译调试，对于学习RS编码原理的人员可以作为一个例子学习，也可以应用于相应的系统中
AES_RTL
- 使用Verilog HDL 實現AES硬體加解密
The_Ten_Commandments_of_Excellent_Design_VHDL_Exa
- This short paper will give you some VHDL code examples that will help you design synchronous circuits that work first time.The philosophy behind Ten-Commandment code is that synthesizers are not to be trusted too much. Most of the code you will see i
jtd
- 用VerilogHDL设计的交通灯控制器，经FPGA验证过-a process based on VerilogHDL is about traffic-light controlling.
UART
- UART串口接受发送，串口调试助手与nexys3进行通信-UART serial ports that accept transmissions