资源列表
assigment3
- Construct VHDL models for 74-139 dual 2-to-4-line decoders using three descr iption styles, i.e., behavioral, dataflow and structural descr iptions. Synthesize and simulate these models respectively in the environment of Xilinx ISE with the Mod
sumador1Bit
- adder/receiver 4 bits
AM30LV0064D_22203
- 介绍了FPGA对AM30LV0064D_22203 NAND FLASH的读写控制，在xilinx下运行通过
mux
- the code is for interfacing camera C3088 with avr microcontroller
xor
- implementation of XOR gate in VHDL with rtl view and simulations
or
- this the vhdl code for or gate with rtl view and simulations-this is the vhdl code for or gate with rtl view and simulations
halfsubtracter
- this the vhdl code for half substractor gate with rtl view and simulations-this is the vhdl code for half substractor gate with rtl view and simulations
halfadder
- this the vhdl code for half adder with rtl view and simulations-this is the vhdl code for half adder with rtl view and simulations
gas-test-cpld
- 瓦斯测试仪CPLD部分程序，采用图表式编程，功能包括I/O扩展、分频、通信等。-The gas tester CPLD part of the program charts programming features include I/O expansion, divider, communications, and so on.
UART-application
- uart核应用的各种介绍 让大家了解到一些基础的知识 总结的很全面 适合初学者-Uart nuclear application of various introduce let everybody understand to some basic knowledge of very comprehensive summary for beginners
vga_char
- verilog实现vga接口，可以在显示器上显示一个字符，具体显示什么字符可以按自己喜好更改相应数据。-verilog vga interface, a character on the display, and specifically what characters can change the corresponding data according to their own preferences.
verilog_uart
- verilog实现串口的调试，用串口调试助手验证通过。-verilog serial debugging and validation by serial debugging assistant.