资源列表
pipelined_computer
- 基于de2-board的汇编以及verilog的五段流水线CPU代码，适合新手学习-Based on the de2-board assembler, and the five-stage pipelined CPU verilog code, suitable for novice learning
adder
- 实现两个一位二进制数的相加，程序简单易懂，特别适合作为quartus ii的练习-a plus b
keyboard
- 实现从键盘输入的vhdl程序，通过按键输入，扫描，键盘去抖动，键盘输出-input from the keyboard
VHDL_commponet
- fpga设计中利用vhdl语言的元件例化语句和程序包可以优化代码，附有加法器，触发器的程序实例-plus and the other devices
ReCOP
- FPGA processor with 23 instructions-control unit of reaction control processor
VHDL
- 表决器 奇校验器 3位比较器 4选1 数据选择器-The odd parity voting 3 comparator election of a data selector
BitStream2SPIAdapter
- verilog code for bit stream adapters
prog
- A simple program for logic gates using KCPSM3 in Spartan 3E Starter kit
VHDL-example
- 利用VHDL语言编写的多个参考程序，适用于各种环境，编程时使用的是altera的开发板-Verilog language reference procedures applicable to a variety of environments, programming altera development board
vga_de_v_2
- 实现了机遇verilog的对LCD屏幕工作在DE模式的刷屏方法-Opportunities verilog on the LCD screen work in DE mode refresh
RunningLED_Flash
- verilog runningled 带flash ,DE2_70 FPGA 开发板运行代码-verilog runningled FPGA DE2_70
HelloWorld
- verilog helloworld 源代码 DE2_70开发板实现LCE显示-verilog helloworld DE2_70