资源列表
fpmul
- floatinfg point multiplier 32 bit parellel processing
XILINXSPARTAN_3Everilog2
- XILINX 的SPARTAN_3E 控制液晶显示屏显示字符串的verilog程序-XILINX 的SPARTAN_3E verilog FPGA use Verilog HDL to display a char on the lcd module lcd_control( input clk,
cycle_code
- verilog实现了MIPS多周期（5周期）的CPU-verilog MIPS 5 cylce
mul64
- Verilog实现的64位乘法器，该乘法器是我所见过的最牛的乘法器、运算快、资源利用少-Verilog implementation of the 64-bit multiplier, the multiplier is the most I have ever seen cattle multiplier, computing faster, less resource utilization
DSPuva16
- * DEscr iptION: DDS design BY PLD DEVICES. * * AUTHOR: Sun Yu * * HISTORY: 12/06/2002 *-* DEscr iptION : DDS BY PLD design Online. * * AUTHOR : Sun Yu * * HISTORY : 12/06/2002 *
Digital-Photo-Frame
- 基于EP1C3T144和sdram的数码相框-EP1C3T144 and sdram-based digital photo frame
lcd
- source code for lcd.c.The header data will be loaded soon after.It is a general lcd c-code.For all types of lcd
ADC0809
- ADC0809是8位AD采样芯片 给大家做子程序用-ADC0809 8-bit AD chips for everyone to do the sampling routine with the
Quartus_Common_Error_And_Warning_Analyze
- Quatus常见错误汇总与分析 该文章来源 :一是来自网上几处出处的汇总 二是来自作者本人应用过程中遇到的问题。 可以帮助大家解决烦人的quartus警告和error 仅供参考 -Summary and analysis of common mistakes Quatus the article Source: First, a summary of provenance from the Internet a few second is from the author
code_ADS_B
- ADS-B发射端RS编码、成帧及相关接口控制代码，通过过板卡测试及验证！-ADS-B transmit side RS coding, framing, and interface control code, through the testing and verification of board
vhdl_example
- 一些vhdl的简单例子。直接解压，不用密码。-instantiate some simple examples. Direct unpack, without a password.
8-1-mux
- 八选一数据选择器，Verilog HDL语言描述，包含文件说明和波形截图-8-1 MUX, Verilog HDL language descr iption ， contains the file descr iption and waveform capture