资源列表
or
- this the vhdl code for or gate with rtl view and simulations-this is the vhdl code for or gate with rtl view and simulations
any-fre
- 任意分频，小数分频，计数分频的源代码，直接使用的模块，，已经在开发中使用过的IP包-Any frequency, fractional frequency count divided by the source code
M25PX_64Mb_Device_Driver
- spi flash 驱动程序 c语言,官方发行版-spi flash c driver
Sdram_Control_4Port.Verilog写的sdram的控制器
- 已经验证可用。此代码为Verilog写的sdram的控制器，可以由用户的使用而加载到自己的项目中自行开发。,Have verified that is available. This Verilog code written sdram controller, can be loaded into the user' s use of their own self-developed projects.
Three-elevator-controller
- 三层电梯控制器，包括发声模块、报警模块、主控制模块、数码管显示模块、分频模块、消抖模块。-Three elevator controller
BH1415
- 数控调频发射器的设计 开关式的锁相环BH1415的调频参考C程序-BH1415 c language for bh1415
supervideolcd
- lcd pic16f877a.is very useful for interdacing
Sdram_Control_4Port
- Sdram Control 4Port Sdram Control 4Port
86verilog
- 以FPGA 芯片为平台构建了数字信号滤波实时处理模块, 给出了 50Hz 陷波器的切比雪夫Ê 型 IIR 数字 滤波器 4 阶级联的结构, 提出了对滤波器系数量化的逼近方法, 完成了基于 FPGA 的陷波器实现, 并成功地实现了 对含有工频 50Hz 噪声干扰的心电信号的滤波处理, 通过与M at lab 计算所得到的滤波处理效果进行比较分析, 结 果表明: 基于FPGA 采用切比雪夫Ê 型 4 级级联结构的 IIR 数字滤波器的误差满足设计要求- W ith t
source
- 使用EP4CE15F17型号的FPGA芯片做的串口协议，使用Verilog HDL完成描述，通过仿真和实验证明功能完好。-FPGA chip using EP4CE15F17 models do serial protocol, using Verilog HDL to complete the descr iption, the simulations and experiments show that function well.
Arduino-Library-for-Proteus
- just a small work taht i made for the network and other thingd
tiling_multi_channel
- This the Tiling multichannel module which used in the JPEG2000 encoder. This module uses the replicated method for boundary extension.-This is the Tiling multichannel module which used in the JPEG2000 encoder. This module uses the replicated method f