资源列表
RS_decoder
- rs编码vvhdl 希望能通过 我不晓得具体对大家有用否 希望懂rs编码的多多交流 -rs coding vvhdl I do not want to be able to know the specific useful whether you want to understand a lot of coding rs exchange
datapath
- for FPGA IMPLEMENTATION,OUR DATAPATH CREATED FOR TWO BIRS MULTIPLICATION-for FPGA IMPLEMENTATION, OUR DATAPATH CREATED FOR TWO BIRS MULTIPLICATION
20k400f672.bsd
- apex20k boundary scan program
windows-script
- 在window平台，采用脚本TCL来编译fpga的经典例子。具体的写法，见工程中的ise_flow.bat文件。如果在工作站来处理更块-In the window platform, using classic example TCL scr ipt to compile the fpga. Specific wording, see the project ise_flow.bat file. If the workstation to handle more blocks
MX25L6445E--Verilog--v1.18
- MX25L6445E开发时间，Verilog语言-MX25L6445E development time, Verilog language
3Channel_CIS_Processor_with-VHDL.ZIP
- This usefull source for control CIS Sensor and has fallowed functions 1) Read image data frome 3channel 200dpi CIS Sensor 2)Encoder Sync Technoledge for more high resolution analiysys with shared the time divition 3)Psudo Video Ram Read by
traffic-light
- 基于vhdl的交通灯设计 包含基础功能 led数码管显示-vhdl traffic light
AD976_6channel
- 软件是适用于FPGA的VHDL程序，目的是用于满足IEC61850－9协议的电子式互感器采样，软件采用的是AD976芯片，能同时进行6个通道的采样。-The software is based on vhdl for FPGA,which is used for electronic transformer fulfil IEC6185-9 protocol.the AD chip is AD976,it works at the state of 6 channels at the same
1602Dynamic-display
- 名称：LCD1602 内容：通过标准程序动态显示字符 引脚定义如下：1-VSS 2-VDD 3-V0 4-RS 5-R/W 6-E 7-14 DB0-DB7 15-BLA 16-BLK-Name: LCD1602 content: The standard procedure for dynamic display of character pins are defined as follows :1-VSS 2-VDD 3-V0 4-RS 5-R/W 6-E 7-14 DB0
conv
- Conv Encoder for VHDL Vivado
DigitalWatch
- Digital watch write in Verilog HDL language simulate the real clock in Atera DE2 development board
DaFilter
- /* This program generates the DApkg.vhd file that is used to define * the DA filter core and gives its parameters and the contents of the * Distributed Arithmetic Look-up-table \"DALUT\" according to the DA algorithm-/ * This program generate