资源列表
pll_use
- 实现了用FPGA调用pll的功能，并在FPGA开发板上实现-Implemented with FPGA calls to the function of the PLL and implementation on FPGA development board
vga_graph_st
- 该程序用vhdl编写的vga显示的小游戏，到时屏幕上会显示一个小球，一根棒子，一面墙，棒子可以通过按键控制来移动。而小球在不停的运动，遇到墙会反弹。-Game written by the program with VHDL VGA display, the screen will display a small ball, a stick, a wall, stick to move through the key control. Ball in constant motion, encou
work_verilog
- 这是用verlog编写的小程序，里面有流水灯，跑马灯，数码管的显示等程序。-This is a small program written using verlog, water lights, marquees, digital tube display program.
cpu
- 本代码主要通过VHDL语言描述了一个CPU，包含了MAR,MBR,PC,BR,ALU,ACC等一系列寄存器。-The code is mainly described by VHDL language a CPU contains a series of MAR, MBR, PC, BR, ALU, ACC register.
vga_interface_requiring_core_regeneration
- vga interface with text rom. font size 80x40. core need core regeneration.
jiyufpgadeshipingcaijichengxu
- 能够很好地进行视屏采集程序，是基于fpga的vhdl语言编程-Can be a good screen capture program, FPGA-based VHDL language programming
HADC
- 简单的高速数据采集系统以及相应的接口电路设计-High speed data acquisition system and interface circuit design
rscode
- R S编 解 码 实 现 代 码 verilog语言-RS CODE AND ENCODE
cpld-usb
- usb-fpga通讯，从cpld到usb协议芯片slave fifo的通讯过程指导。-The usb-FPGA communication from the CPLD to usb protocol chip slave FIFO communication process guidance.
vhdl-code-for-FFT-32-point
- vhdl code for FFT 32 point
prj_5
- FIFO Using MyFIFO_Block_Memory_v7_1 with verilog code
prj_2
- a practical project using blk_mem_gen_v7_1_Veriloge