资源列表
develop_frame_find
- 基于FPGA中OFDM中的帧检测，由于采用简化算法，采用较少的复数乘法器，易于硬件实现，且节省资源，采用verilog实现.-Frame detection based on FPGA for OFDM, a simplified algorithm, using less complex multiplier, easily implemented in hardware, and save resources, the SNR performance is slightly lower th
develop_Phase_Tracking
- 基于FPGA实现，OFDM基带通信中的剩余相位检测，具有很好的性能，采用verilog语言。-FPGA-based the remaining OFDM baseband communication phase detection, has a very good performance, verilog language.
cntm60v
- 基于VHDL的60进制计数器代码，可以实现六十进制计数-60 binary counter based on the VHDL code can be achieved sexagesimal counting
ImageRotate
- 利用verilog实现图像旋转。本程序是基于XILINX公司的ISE实现的。-Verilog image rotation. This procedure is based on XILINX' s ISE.
sequence_detect
- 串行数据检测器，检测数据中是否存在10010，用FSM编写，在modelsim中仿真通过，功能上符合要求-Serial data detector detects data exists 10010, with FSM write, through simulation in modelsim functionality required
syn_FIFO
- 同步FIFO，主要用于数据缓存，给异步FIFO打下基础，是个不错学习例子，在ncverilog中仿真通过-Synchronous FIFO, mainly used for the data cache, and lay the foundation to the asynchronous FIFO, is a good example of learning through simulation in ncverilog
drink_sell_machine
- 用verilog HDL编写的投币机，能实现单种饮料的够买找零-Written in verilog HDL slot machines, enough to buy a single beverage give change
fpga_Stepper-motor
- 通过状态机控制步进电机的转动方向和转动角度-Through the state machine to control the direction of rotation of the stepper motor and the rotation angle
16f630
- hi impedance remote control ir circuits
Synthesis-and-Simulation
- Synthesis and Simulation Design Guide，Xilinx公司的FPGA逻辑综合与仿真，英文版的。-Synthesis and Simulation Design Guide
my-scaler
- 图像缩放源代码，该代码支持输入bmp文件格式，输出bmp格式。-Image scaling source code, which support the input bmp file format, the output bmp format.
dataflow-description
- 这个文件给出了一个四位比较器的数据流描述算法。-This document gives a four comparator data flow descr iption algorithm.