资源列表
uart
- UART verilog 代码， 内置CPU接口方式，支持2线制和流控4线制。支持轮训和中断方式。-UART verilog source code
DDS
- dds的源码，可以合成任意波形，VHDL语言-dds source, we can refer to very good
altera-IPCoreLicense
- alteraIPCoreLicense ,altrea IP和的 license。-alteraIPCoreLicense, altrea IP and the license.
gray_data
- 本程序可自动产生数据，存入存储器中并转化为格雷码，按时序输出。-This program can be automatically generates data such as the memory of deposit and translated into gray code, and the output time sequence.
source
- A basic DMA Controller source code
i2c_verilog
- FPGA读写i2c的内部数据基于verilog语言的描述，按照内部时序访问-I2c data read and write the internal FPGA verilog language based on the descr iption, in accordance with the internal timing to visit
fft256_512_1024
- 基于基2的并行256，1024深度的FFT源代码verilog-Based on radix-2 FFT parallel 256,1024 depth verilog source code
PV_Single_Phase_bingwang
- 包括PV模块，MPPT，并网系统， mdl格式，且是单相并网 。-Including PV modules, MPPT, grid system, MDL format, and is a single-phase grid.
Pseudo-Random
- Pseudo Random Sequence Generator Code and Tutor
VGA_color_block
- 在FPGA上采用Verilog语言，通过VGA接口实现彩色条显示-On FPGA using Verilog language, color bar display via VGA interface
source9-10
- verilog hdl教程135例:verilog hdl语言类似于C语言，便于学习。本文档带有源代码，9-10章-Verilog HDL 135 cases Guide : Verilog HDL language similar to the C language, to facilitate learning. This document with the source code, 9-10
ddr_dimm
- 256Mb_ddr 实现ddr_dimm操作-256Mb_ddr achieve ddr_dimm operation