资源列表
Audio_DAC_FIFO
- 用于做多媒体缓存的源码 可以做整帧的缓存-SquiDeral- manipulating the cache usage of Your Audio.
UP3_CLOCK
- 一个很小的时钟代码 一个很小的时钟代码-a small clock code, a small clock code, a small clock code a small clock code
VERILOGSELE
- 运用always 块设计一个八路数据选择器。要求：每路输入数据与输出数据均为4 位2进制数，当选择开关(至少3 位)或输入数据发生变化时，输出数据也相应地变-always use a block design options for the Eighth Route Army data. Requirements : every road input data and output data are four two-band number, When choosing to switch (a
hdlsrc
- ofdm transceiver code
LCD1601
- ＬＣＤ１６０１在８０５１上的驱动，可在屏幕上显示任意字符-LCD1601 driver in 8051 can be any character on the screen
sd_slave_device
- verilog source code for SD card SLAVE DEVICE IP-Core
code
- 一个基于fpga的简单的实时心电检测系统，包括与pc通讯和qrs检测两部分-A simple fpga-based real-time ECG detection system, including communication with the pc and qrs detection of two parts
mips
- Verilog语言开发的基于mips指令集的流水线cpu，只支持部分指令-Verilog language-based development pipeline cpu mips instruction set support only part of the instruction
PS2-mouse
- 用VHDL语言实现一个简单的PS/2接口鼠标的控制，下载到FPGA芯片中，实现鼠标初始化，并对鼠标数据传输进行监控，输出一个鼠标光标地址和按钮状态。-With VHDL a simple PS/2 interface mouse control, downloaded to the FPGA chip, the realization of the mouse initialization, monitor and mouse data transmission, the output of a
tutorial
- another verilog VHDL tutorial, targeting altera DE2 board, but very intuituve.
wb_conbus.tar
- wish brone总线代码，用于FPGA内部各模块连接-wish brone bus code for internal FPGA modules connected
200712312258925928
- 整点闹钟，可以实现整点闹铃的功能。该程序是本人从其他地方找到了，非本人的