资源列表
zhengxuanbo
- 产生正弦波的vhdl代码，输出显示波形标准，没有明显的波形失真。-Vhdl code for sine wave generation, the output waveform standards, no significant waveform distortion.
create_pulse
- 使用 verilog hdl 创建指定频率的脉冲-create the fre with verilog hdl
test_com
- 本实验是用来测试FPGA和串口之间的通信的，FPGA发数据读串口的写数据，再发到串口显示出来。-This experiment is used to test the communication between the FPGA and the serial port of, FPGA send data read write serial port data, and then sent to the serial port is displayed.
song
- 基于verilog实现的音乐程序，很好听啊-Verilog implementation based on the music program, good to hear ah
acquisition_ad9887a1.3
- FPGA 将ad9887a输出的数据写入FIFO_00中，并计数输入的点频，行频和当前行频。将计数的点频，行频和场频数，以及行场信号输出信号（高电平有效）。 点频计数值为前一行的数据量。行频计数输出是前一场的计数。当前行频计数输出是当前行在这一场的行数。-FPGA will ad9887a output data is written FIFO_00 in and point counting input frequency, line frequency, and current line
ljj
- hs0038的红外接收程序，用于接收遥控器的信号-the driver for hongwai receive
DENG-JING-DU
- 基于FPGA的等精度频率计设计，实现百万分之一的误差精度-FPGA-based design and other precision frequency to achieve the accuracy of one millionth of error
mobilephon-sound
- this is musicbox mobilephon bell sound is played by this code
xapp856
- 基于FPGA的SFI接口实现（VHDL，Verilog and doc）-SFI-4.1 16-Channel SDR Interface with Bus Alignment
ModelSim
- verilog Source code for DCT
time
- Verilog语言编写的，利用分频定时器的方法在数码管上显示0-59 按秒显示。-Verilog language, the method of the dividing timer is displayed on the digital display 0-59 seconds.
ping_pang
- 编写的乒乓球游戏程序，包括原文件和仿真文件等，注释详细-Writing table tennis games, including the original files and simulation files, detailed notes