资源列表
ead
- VHDL设计初步，一些基本的程序。希望大家支持学习。-VHDL design of a preliminary, some basic procedures. I hope you will support learning.
100-FPGA-questions-Download
- FPGA经典100问之＜下载验证16问＞。介绍了FPGA在下载验证过程中的常见问题，对FPGA常见配置电路进行了讲解。-FPGA asked the classic 100 < Download verified 16 Q> . FAQ introduced FPGA verification process the download of FPGA configuration circuit common were explained.
eda
- 一百进制计数器，以十进制计数器为模板增加十位计数，可类比写出多位计数器。九十九清零。-One hundred binary counter, decimal counter increased ten count as a template, you can write a number of analog counter. Ninety-nine cleared.
decimal_divison
- 使用双模计数器实现的FPGA小数分频器，语言verilog HDL。-FPGA implementation using dual-mode fractional divider counter, language verilog HDL.
07-part05
- multiplier, VHDL verilog file
verilogiic1121
- fpga通过i2和e2prom通信，调试通过，可以直接拿来用-the test is ok
shizhong
- verilog 语言编写整点报时的数字钟-verilog clock with hourly chime function
key_board
- 刚刚调试好的，好用的fpga接收ps2键盘程序-A nice fpga receive ps2 keyboard program
yibutongxin
- 用VHDL编写的串口异步通信的例子，适于RS232、RS422的通信
RS_Decoder
- RS的解调编码，已经运行过，正确无误，学习使用-RS demodulation code has been run over, correct, learning to use
queue
- 完成FIFO功能：the first element added to a queue will occur in the first place in the queue, the second element added to the queue will be after the first one-a kind of First-In-First-Out (FIFO) data structure，the first element added to a queue will occ
IRDATA
- FPGA接收红外线，Verilog代码，完整的工程-FPGA to receive infrared, Verilog code, complete the project