资源列表
Auto_elect_ticket_machines
- 数字逻辑的自动电子售票机的quartus编程。-Digital logic quartus automatic electronic vending machine programming.
FPGA-websites
- 常用FPGA网站，国内的和国外的，比较实用。-useful FPGA websites
RS(204188)
- RS(204,188)译码器的设计，经典实例，经过验证-RS (204,188) decoder design, the classic instance of proven
doc
- the document is used yo known the university
9.59
- 实现9分59秒的记时功能 当输入1Hz的脉冲时，且START置1时，能正常记时，当将RESET置1时，可以实现复位功能 当将STOP置1时，可以停止记时，记时的能记到9分59秒-9 minutes and 59 seconds to achieve when the mind functions when the input pulse 1Hz, and START is set to 1, to normal mind, and when the RESET is set to 1 w
spi-verilog
- 用Verilog来实现SPI接口电路逻辑，实现主机与从处理器的通信-SPI interface circuit is implemented in Verilog logic between master and slave processor communication
sopc_avalon_audio_dac_fifo
- fpga嵌入式系统组件，可以很方便的扩展，是个实例的例子，可以实现歌曲播放
i2c
- 基于51的IIC程序 模拟IIC的 希望对你有帮助-51 IIC procedures based on hope to help you
des1
- 对称密码算法des的Verilog语言实现，已经测试通过。欢迎下载！-Symmetric cryptographic algorithm of des Verilog language implementation, has the test pass. Welcome to download!
sicengdianti
- 用VHDL语言编写的四层电梯控制器，可以实现四层电梯控制-Four-story elevator controller
RS_bmq
- 在QuartusII软件中用Verilog HDL编写的RS编码器的源代码-The RS encoder Verilog HDL prepared with in QuartusII software source code
JK-flip-flop
- 带有异步置位复位端的上升沿触发的JK触发器，使用VHDL语言实现的-Asynchronous reset terminal set with rising edge triggered JK flip-flop, the use of VHDL language