资源列表
Based-FPGA-digital-clock-design
- 基于FPGA的数字时钟设计，这里是我做的一个电子时钟，大家可以借鉴一下！-Based FPGA digital clock design
CPLD-code
- CPLD开发板实验代码，包括Verilog和VHDL源代码，原理图-CPLD development board experimental code, including Verilog and VHDL source code, schematics
verilog-ip-core
- verilog ip核，源代码，ethernet， video_compression_systems-verilog ip core source code, ethernet, video_compression_systems
adder_s
- 八位并行加法器，同时进位，利用VHDL语言，在ISE环境中建立工程-Eight parallel adder
Sender
- 直序扩频通信发送部分的源代码，用verilog编的，包括信源模块、扩频模块、极性变换模块和DDS调制模块-Direct sequence spread spectrum communication sent part of the source code, compiled with verilog source modules, spread spectrum modules, polarity transform module and DDS modulation module
conversions
- 我在尝试上传一系列对初学者有用的code。 该code可以帮助学习者学习如何用VHDL进行信号类型的转换-I m trying to upload a series of useful code for beginners. The code can help learners to learn how to use VHDL achieving signals type conversion
operators
- 我在尝试上传一系列对初学者有用的code。 这个程序描述了如何运用VHDL中的部分运算，如“左移”，“右移”，“按位取反”等-I m trying to upload a series of useful code for beginners. This code describes how to use the operator in VHDL, such as "left shift" "right shift" "bitwise inversion"
Dff
- D 触发器，数字电路中最基本的逻辑单元之一。很实用的程序例子-D flip-flop, one of the basic logics in the digital design, an instance of a Sequential VHDL codes
FPGAgame
- 基于FPGA的俄罗斯方块VHDL逻辑代码，通过VGA显示在液晶屏幕上，基本功能完全实现-VHDL logic code Tetris FPGA-based VGA display on the LCD screen, the basic functions of the full realization of
43Panel_Logic_Driver
- 4.3寸彩屏的Verilog 逻辑驱动程序-4.3-inch color screen Verilog logic driver
qidaqiFPGA
- Verilog 编写的纯逻辑四路抢答器，一位主持人控制按钮与四位抢答者控制按钮协同工作-Verilog prepared by the the Pure Logic Quad Responder, a moderator control button with four Responder the control buttons collaborative work
OscilloscopeVerilog
- Verilog 编写的纯逻辑便携式示波器，具有良好设计代码风格以及功能质量-Verilog written in pure logic portable oscilloscopes with good design code style and functional quality