资源列表
fenpin
- 时钟分频器，初学者可以下载学习，效果比较好-Clock divider, beginners can download the study results were quite good
ep1c6_29_dds
- 此程序为一实现DDS的程序，很好的用VHDL语言编写。-this is a dds program by VHDL .Tt is a very accutate program.
asyncRst
- 异步复位的同步化处理，对于asic设计尤为重要-Asynchronous reset the synchronization processing is particularly important for asic design
zmstz
- 用Verilog HDL语言实现正码速调整的功能，并通过Quartus Ⅱ 功能仿真验证-Verilog HDL language used is code rate adjustment function, and functional simulation by Quartus Ⅱ
kbmjsq
- 用Verilog HDL语言实现可变模计数器的功能，并通过Quartus Ⅱ 功能仿真验证-Variable with the Verilog HDL language to counter the function module and function through simulation Quartus Ⅱ
s_p
- 用Verilog HDL语言进行并串转换，并通过Quartus Ⅱ 功能仿真验证-With the Verilog HDL language and string conversion functions through simulation Quartus Ⅱ
p_s
- 用Verilog HDL语言进行串并转换，并通过Quartus Ⅱ 功能仿真验证-Series with the Verilog HDL language and converted, and through functional simulation Quartus Ⅱ
FPGAExamples
- 列举了一些FPGA的常用实例，有助于加深对FPGA的了解-gfdhgfhgfdgvfhgfhgjngh
c3
- VerilogHDL编写的8位加法器实现-bgfhgfhjgjhgj
my_walkled_v3
- 自动跑马灯 开发板采用stratix4系列开发板 可以使用开关控制跑马灯方向-LED WALKING
auart_send
- usb command 静态存储器源程序-usb command
timer
- 外设timer设计：16bit定时器、ETU计数器、具有3种可配置中断请求输出、内部寄存器的读写编程。-Peripheral timer design: 16bit timer, ETU counter, with 3 configurable interrupt request output, the internal register read and write programming.