资源列表
sin_gnt
- 用FPGA实现的正选信号发生器，可以用于后续实验的信号源-sin_gnt
SHIFTER
- 使用VHDL语言编写的移位加法器，经过硬件实现通过-shifter
Demultiplexer
- 解复用器，很好很强大的程序 解复用器，很好很强大的程序-DEscr iptION : Demultiplexer -- Width: 8 -- Number of terminals: 4 -- Output enable active: HIGH -- Output active : HIGH
Verilog
- 东南大学Verilog HDL经典讲义，有助于初学者的学习-Southeast University, Verilog HDL classic lectures to help beginners learn
source
- VerilogHDL的一些典型应用例子，附带程序-VerilogHDL examples of some typical applications, with programs
viterbidec
- 关于fpga的论文，很有使用价值，希望大家能用的上。-Papers on the fpga, great value, I hope everyone can be the last.
verilog_EXAMPLE
- verilog编写的例程指导，包括入门教程和一些设计实例-verilog routines written guidance, including the Getting Started tutorials, and some design examples
series_port
- 用verilog语言编写的串口收发程序，可以进行429总线数据与rs232口的通信。-With verilog program written in serial transceivers, can be 429 bus data and rs232 mouth communication.
m_vhdl
- 设计一个伪随机序列发生器，采用的生成多项式为1+X^3+X^7。要求具有一个RESET端和两个控制端来调整寄存器初值（程序中设定好四种非零初值可选）。-Design a pseudo-random sequence generator, using the generating polynomial 1+ X ^ 3+ X ^ 7. Requires a RESET terminal end and two control registers to adjust the initial valu
sine_vhdl
- this a snipet of code about the sine generator implementation in vhdl-this is a snipet of code about the sine generator implementation in vhdl
bcd_to_binary
- bcd to binary verilog
Decoder
- This a basic code for the decoder based on verilog.-This is a basic code for the decoder based on verilog.