资源列表
adder_8
- altera cylon的8位加法器设计，已经通过综合了，可以下来测一下-a simple of the 8 adder for altera FPGA
Verilog
- 东南大学语言讲义，希望对你有帮助 很好的资料-Southeast University, language notes, I hope you have good information to help
12354
- FPGA的中文使用手册，很使用，上传给大家共享，希望喜欢-FPGA' s Chinese user manual, it is used to upload to share the hope that like
1111111
- FPGA与I2C总线器件接口设计，东西不错，给大家分享-FPGA devices with I2C bus interface design, something good to share
fpga111
- 基于FPGA步电机毕业设计的开通报告，共享给大家，希望有用-Step Motor Based on FPGA opening graduation report, shared with us the hope that useful
image_download_demo(valid20091129)
- DE1上实现数码相框的verilog代码，以及实现方式-DE1 digital photo frame to achieve the verilog code, and Realization
51_timer
- 51_TIMER的verilog实现，在DE2板上验证-51_TIMER the verilog implementation, the DE2 board certification
DE2_TOP_ps2_mouse
- ps2_mouse实现的源代码，在Altera的DE2板上实现-ps2_mouse the source code, implementation in Altera' s DE2 board
DE2_TOP
- ps2_keyboard的实现方式，在Altera的DE2板上实现-ps2_keyboard for implementation, implementation in Altera' s DE2 board
ac97_latest.tar
- ac97的verilog实现，包含详细的代码实现以及仿真，非常可靠-ac97，verilog rtl
spi
- 串行外围接口，可用于FPGA器件与串行A/D/A的通信-Serial peripheral interface, which can be used for communication between FPGA devices and serial A/D/A
key-dejitter
- 按键去抖模块，避免按键抖动引起的系统误操作。FPGA时钟频率25.000MHZ-Key de-jittering module to avoid system misoperation caused by key-jitter. FPGA clock frequency 25.000MHZ