资源列表
nco11000
- 实现输入一正弦波和噪声的叠加，介绍详细欢迎下载-The input of a superposition of sine wave and noise introduced in detail
my_gold
- 基于FPGA的gold码发生器，用VHDL语言编写的源程序。-The gold code generator based on FPGA, VHDL language with the source.
lvds
- 文章介绍了lvds技术在硬件设计中的原理和应用，先已被广泛应用-This paper introduces lvds in hardware design and application of the principle, first has been widely used
vhdl_pedroni
- a book for Vhdl. which contains basic programs and also the state diagram programs
vgaclock
- source code clock for vga sistem
lab1
- DE2开发板配套LAB1里面源代码，一共六部分。-DE2 development board s source of lab1,which is seperated to 6 parts.
VHDL_statemachine
- MOORE 和MEALY模型的状态机，用VHDL语言描述，本章讲述状态机实现的原理以及方法，希望对大家有用，同时有练习题和思考题-MOORE and MEALY model state machine, using VHDL language descr iption of the state machine implementation of this chapter describes the principle and method, we want to be useful, while
ram
- 实现了对于SRAM的读写控制输入和输出，能够连续的进行读写操作以及能够对各种四则运算的嵌入-Achieved for the SRAM read and write control input and output, can continuous operation and can read and write all four of embedded computing
vhdl
- 伪随机序列发生器得VHDL语言源代码，已通过仿真。-Pseudo-random sequence generator may VHDL language source code, by simulation.
Proyekton
- Alarm clock vhdl gdf for MAX2+plus
JK
- 一个JK触发器 虽然比较简单 但或许会对你有用 里面代码跟仿真都有-FPGA
FPGA1
- 4位全加器 仿真波形一点问题都没有 我调试过-ADD