资源列表
huoqucpuxuhao
- 查看cpu序号 可以使软件绑定电脑 方便我们自己辛苦编写的软件使用合法-View cpu serial number
data_interleaver_ise10migration
- ofdm通信系统交织的Verilog实现，源码中有两个错误，第二处少了一个begin 第一处为全角半角，自己写一下就行-ofdm data_interleaver
jiaozhiqi
- 是Turbo码交织器的VHDL设计与仿真的文献-Is the Turbo Code Interleaver Design and Simulation of VHDL literature
s3en_tcp
- 基于spartan3e开发板的嵌入式EDK软件平台下的TCP/IP协议的网口程序-Embedded development board based on spartan3e EDK software platform for TCP/IP protocol network port procedures
DE2_USB_API
- USB画笔，基于altera de2平台，全都有啦，很好的例子-USB brush, based on altera de2 platform, all have friends, a good example. .
vga_game_demo
- 基于FPGA的乒乓球游戏参考设计-FPGA-based reference design table tennis game
a
- 讲述了如何使用ModelSim与Quartus结合进行时序仿真 -Describes how to use ModelSim for timing simulation combined with the Quartus
soundfft
- 使用labview编写音频FFT算法程序，调试好用的-Sound FFT program of Labview
vhdl
- 基于FPGA的等精度频率计 频率测试功能：测量范围1Hz～20MHz。测频精度：测频全域相对误差恒为万分之一基于FPGA的等精度频率计-based on FPGA precision frequency meter
UART_IP_core_for_wishbone
- 基于wishbone总线的UART IP core-UART IP core based on Wishbone, generated in Verilog HDL.
ml505_mig_design
- Xilinx开发板ML505的DDRII示例程序，使用Verilog，调用MIG，编译环境ISE11.1-Xilinx ML505 development board of DDRII sample program, using Verilog, called MIG, build environment ISE11.1
Verilog
- verilog 大量源代码 verilog 大量源代码