资源列表
testbench
- 介绍了fpga设计中，利用testbench设计源码测试激励文件，很方便很详细-Introduced fpga design, test stimulus using testbench design source files, it is more convenient
FSM
- 有限状态机设计指导,详细介绍了设计状态机过程中的有关经验，以及各种状态机设计的相互优劣对比-Finite state machine design guidance, details of the design state machine during the relevant experience, as well as various advantages and disadvantages of each state machine design comparison
RS-5-3-CODE
- RS(5,3）编码器原程序 程序已经调试过 且比较简短-RS(5,3） coder ,this code is very short
RS_255_223_ENCODER
- RS(255,223)编码器程序 从一本书上看到的，很不错的-RS(255,223) encode , very good good good
crc_snd
- 串行数据的CRC校验，输出16位CRC校验码，通过仿真-CRC check serial data output 16-bit CRC check code, the simulation
61EDA_C2714
- xilinx ISE 4.1的入门，简单简单的。看看看看！-xilinx ISE 4.1, entry, simple simple. Look look!
characters
- 一个是发送单个字符的，一个是发送任意长度字符串的-One is to send a single character, a string of arbitrary length is sent
SRAM
- SRAM源代码，VHDL语言编写，载入可编译，需要的-SRAM source code, VHDL language, incorporated in the compiler, we need to see
comp
- 经典比较器源代码，VHDL语言编写，可以-Classic source code comparator, VHDL language, you can see
fulladde
- 全加器源代码，VHDL语言编写，有需要的参考参考-Full adder source code, VHDL language, the need to reference information
half_adde
- 半加器源代码，用VHDL语言编写有需要的可以-Half adder source code, using VHDL language need to look at
ofdm
- ofdm调制解调的fpga实现。使用Verilog实现IEEE 802.16a系统的调制解调模块。-ofdm modulation and demodulation of fpga implementation. Verilog implementation using IEEE 802.16a system, modem module.