资源列表
vsb
- modulation in matlab
timer
- 通过使用Nios_II环境，实现一个定时中断器的应用。-By use Nios_II environment, a timer interrupt applications.
processor
- 通过verilog语言编程实现简单的微处理器，实现简单的加减和复制功能。-Through the verilog language programming simple microprocessor, simple addition and subtraction, and copy functions.
untitled3
- 篮球24秒计时器，实现24秒计时，每到24秒蜂鸣器报警-Basketball 24 second timer 24 seconds, every 24 seconds a buzzer alarm
Bin2Bcd
- 要是想实现任意一个数在LED上显示出来，比如201111，它在内部是以二进制形式存在的，我想在六个七段LED显示灯上分别显示2、0、1、1、1、1，这个代码能够实现这个功能。-If we want to achieve any number displayed on the LED, such as 201111, it internally in binary form there, I want to show the six seven-segment LED display lights
ucos_led
- 这是用sopc搭建的一个工程，利用移植的ucosII操作系统，实现两个led同时亮-This is a project built with sopc utilize a transplant ucosII operating system, two led simultaneously bright
niosii-triple-speed-ethernet
- 这是用sopc搭建的一个工程，实现三速以太网的传输。开发版是3c120-This is an engineering sopc structures, triple-speed Ethernet transmission. The Developer Edition is 3c120
source
- altera DDR3 逻辑测试代码，这是工程实际调试好的代码，保证能用。-altera DDR3 vhdl code
S8_UART
- FPGA串口Verilog程序，用的芯片是xilinx spantan6-The FPGA serial Verilog the program chip with xilinx spantan6
S16_ADC
- 基于xilinx的vhdl采集程序，芯片为AD7923-Based on the xilinx vhdl collection procedures chip AD7923
LCD1206
- 用于lcd1206的显示代码 通过quartus验证-For lcd1206 display code by quartus verify
dianti
- 电梯程序 用verilog实现 经过quartus验证-Elevator after quartus verification procedures with verilog