资源列表
vslides
- 超级经典的面向最终结构优化的verilog编码模式，必须推荐。-a reference for writting optimized verilog code
FPGA-based-embedded-system-design
- 基于FPGA的嵌入式系统设计-FPGA-based embedded system design
SIN001
- sin函数波形发生的VERILOG语言原代码-the VERILOG language original code sin function waveform generation
uart
- veilog 实现FPGA的串口收发器，自发自收，稍作修改可以用于单独发送和接收模块。-verilog describe uart
manchester
- 使用VHDL语言编程，在FPGA上实现曼彻斯特编码，可用于通信领域编码。-VHDL language programming, implemented on FPGA Manchester encoding can be used in the communication field coding.
chap3
- 这是特权同学的实验二 分频计数器的实验代码-this is code about FPGA
NIOS_USBDEVICE
- FPGA QUARTUS USB总线通讯模块程序，常用模块。-FPGA QUARTUS USB bus module ,written by vhdl tools,a useful module.
NIOS_EPROM
- fpga USB主机实现例程，黑金开发板自带。 -fpga USB host to achieve the routine black gold development board comes with
NIOS_USBHOST
- FPGA QUARTUS USB设备通讯模块程序，常用模块。-FPGA QUARTUS USB devive module ,embeded device.
verilog 源代码
- DE2 开发板 PS2 1602 LCD 串行 传输 显示
display
- VHDL写的万能数码管显示电路，在板子上下载跑过-VHDL write universal digital display circuit
Reconfigurablefliter
- 自己编写的SystemC源代码，拥有五级流水线的可重构图像滤波器，支持两种图像滤波算法，中值滤波和邻域平均滤波，支持算法配置-I have written SystemC source code, the reconfigurable image filter has a five-stage pipeline, supports two types of image filtering algorithms, median filtering and neighborhood average