资源列表
DE2_Simple_Socket_Example
- DE2板子上的Simple_Socket_Example，可以供大家参考-DE2 board Simple_Socket_Example, for your reference
cpu
- 用verilog语言写的简单cpu，在处理器功能和结构上，对于初学者有很大帮助。-Verilog language write simple cpu, processor function and structure of great help for beginners.
tetrix
- 基于EXCD-1开发板的VHDL语言开发程序，用以实现俄罗斯方块游戏的设计的功能。-The VHDL development program based on the EXCD-1 development board to achieve Tetris game design function.
CPU_Sinple
- 实现单周期CPU，完全按照设计图设计出各个部件后用函数联合成CPU。-Function joint completely designed in accordance with the design of the various components to achieve single-cycle CPU to CPU.
recive-input-from-standard-keyboard
- FPGA开发板可以接受标准键盘的输入并且将输入的字母现实到数码管上。-FPGA development board can accept standard keyboard input and the input letters realistic digital tube.
rtl
- This is also RTL of router by using another type of method
check
- 这是一个检测器，功能是可以检测输入信号里面“1111”序列的vhdl程序。-This is a detector, the function is the sequence of " 1111" of the input signal which can be detected vhdl procedures.
NIOS_LCD
- FPGA NIOS 操作系统下的液晶驱动程序，黑白点阵。-FPGA NIOS LCD DRIVER ROUTINE
addsub32bit
- 32bit floating point addition
shumaguandongtai
- VHDL的动态扫描显示六个数码管，包含分频代码产生25kHz的扫描信号作为时钟。-VHDL dynamic scanning display six digital tube contains 25kHz scanning signal is generated as a clock divider code.
clock
- verilog编写的8位数码管时钟，可现实秒，分，时-8 digital tube clock written in verilog reality of seconds, minutes, hours
traffic
- 东南大学信息学院大三编程课，VHDL相关交通灯大作业相关代码。欢迎指教改正-Southeast University, School of Information junior programming class job code for the VHDL traffic lights. Welcome advice corrections