资源列表
bps
- ＦＰＧＡ的运用：基于ｖｅｒｉｌｏｇ的任意波特率配置模块-The application of FPGA: Based on Verilog arbitrary baud rate configuration module
VHDL_qicheweideng
- VHDL语言，汽车尾灯的设计 设计说明：共6个尾灯，汽车正常行驶时，6个灯全灭； 左转时，左边3个灯从右到左依次亮灭； 右转时，右边3个灯从左到右依次亮灭； 刹车时，车灯全亮；故障时，全部闪烁。 -VHDL language, the design of the design of the taillights Descr iption: six taillights, the normal running of the vehicle, six lights all off
Bubble-Sorter
- 冒泡排序算法的verilog实现，基于FPGA-Verilog implementation of the bubble sort algorithm, based on FPGA
ise1
- ise教程,Xilinx FPGA/CPLD设计手册 Xilinx公司推荐FPGA/CPLD培训手册-ise for Xilinx FPGA/CPLD
design
- I2C总线的fpga实现，完整工程，已验证通过-Fpga implementation of the I2C bus, complete engineering, has been verified through
clkdiv
- 任意分频电路的verilog实现，包含奇分频和偶分频-Arbitrary divider circuit verilog achieve, contains odd and even frequency divider
wendu
- 基于FPGA和DHT11的温湿度采集系统-Acquisition system based on FPGA and DHT11 temperature and humidity
aa
- 这个程序就是序列检测器的vhdl实现，真麻烦啊-This program is the sequence detector vhdl achieve real trouble
uart
- 基于XILINX+ISE的通用串行总线设计-Design based on the Universal Serial Bus XILINX+ISE
USB
- 基于XILINX+ISE+14.1的usb协议设计-Usb protocol design based on XILINX+ISE+14.1
lcd
- 控制LCD1602显示的VHDL程序 自带延迟和1602字库-Control LCD1602 displayed VHDL program
shi-zhong
- 基于fpga的时钟设计，包含报时模块，时段控制，等-Fpga-based clock design contains timekeeping module, time control, and so on. .