资源列表
pll
- 用verilog实现奇数分频器程序，通过仿真验证-Odd divider program is verified by simulation with verilog
Modelsim-setup
- vhdl开发环境之----modelsim安装步骤-VHDL development environment---- modelsim installation steps
Three-voting-machine
- 三位表决器，源代码-Three voting machine
SAR_Send
- 对altera的RS编解码IP核进行仿真，并且写了编解码的控制模块，用verilog实现，通过仿真，编码和解码功能正确。-test of RS code and RS decode,by using quartus ii9.0 with the IP core
picoblaze
- picoblaze top level entity for xilinx
add_ded_module
- 使用Verilog语言编写的4位加减法器，经验证能在FPGA开发板上实现。-Verilog4 bit adder-subtractor.
switch
- 运用VHDL语言，实现MAX7317的采集程序，可以将该子模块加载到主程序中。-The use of VHDL language the MAX7317' s acquisition program, this sub-module is loaded into the main program.
2LCD1602A
- FPGA VHDL 2LCD1602A VHDL实现-FPGA VHDL 2LCD1602A
add
- 用verilog实现加法器程序，通过仿真验证-Adder verilog achieve program is verified by simulation
adc
- 实现模数转换功能,采样频率为时钟频率的36分之1，可以双路同时采样，并且串行输出，输出数据14位有符号数。-The analog-to-digital conversion, the sampling frequency is 1/36 of the clock frequency, can be dual simultaneous sampling, as well as serial output, the output data 14 of the number of symbols.
xmtr
- 运用VHDL语言，实现串口的发送子程序，可以将该模块直接套入主程序。-VHDL UART SEND
johnson
- johnson计数器是一种同步计数器，每一次之变化一位，具有最简的组合逻辑电路。-johnson counter is a synchronous counter, each followed by a change, with the most simple combinational logic circuit.