资源列表
serial_in_vhd_data_conversion.
- signal data conversion,signal data conversion
edge_detect
- 采用VHDL语言编写的边缘检测源代码，在xilinx公司的spatan-3an的仿真版上验证无误，供初学者学习-Edge detection using VHDL language source code, verification, simulation version of the company spatan-3an xilinx for beginners to learn
grlib-gpl-1.1.0-b4113
- gaisler开发一些免费可以使用的ip集合，我们很多常用的ip代码都可以在其中找到。-gaisler developers can use for free ip collection, many of us used the ip code where you can find.
first
- 3-8译码器：输入变量为三个A,B,C，输出变量有8个，即Y0~Y7。 G1,G2A,G2B为选通输入，仅当G1=1, G2A=0, G2B=0时，译码器能够正确输出，否则，译码器输出无效，Y0~Y7均为高电平“11111111”。 -The 3-8 decoder: input variables for the three A, B, C, the output variables are eight, i.e. the Y0 ~~ Y7. G1, G2A, G2B strobe
sipo_vhd.zip
- serial in parallel out using vhdl,serial in parallel out using vhdl
AMBA_SPEC
- AMBA标准2.0版本，包括AHB，APB和ASB-AMBA standard specfication rev2.0, including AHB, APB, and ASB
6678_pci_duplex
- PCI9656 的控制，ISE 12.2，verilog编写，slave模式-PCI9656，verilog，ISE 12.2，using verilog，SLAVE mode
DDSVHDLCODE
- 本人收集的多个VHDL语言编写的正弦波发生器以及SPWM程序。-I collected multiple VHDL language of sine wave generator SPWM program.
led_key
- LED七段数码管键控显示，通过矩阵键盘控制，-LED nixie tubes keying display,using matrix keyboard controlling
SMBus_Controller
- 基于MAX系列CPLD的SMBUS控制器工程文件。代码为VHDL代码-The the SMBUS controller works based on the MAX series CPLDs file. Code for VHDL code
batch-26.rar
- IMPLEMENTATION OF SOME VHDL AND VERILOG PROGRAM IN FPGA.,IMPLEMENTATION OF SOME VHDL AND VERILOG PROGRAM IN FPGA.
control_pipeline.zip
- Verilog components for a pipelined cpu simulation,Verilog components for a pipelined cpu simulation